EPM7128STC100

IC MAX 7000 CPLD, 100-TQFP, High-performance, PCI-compliant, -2.0 to 7.0 V Supply voltage

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Price:: US $0.10~100.00 / piece [Get Latest Price]

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PartNumber:: EPM7128STC100

Brand:: Altera Corporation - ALTR | Pack: SMD | D/C: 11+

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Products Upload time: 2011-11-30

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Product Summary

The EPM7128STC100 high-density, high-performance PLD is based on second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7128STC100 provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. The EPM7128STC100 in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.

Parametrics

EPM7128STC100 absolute maximum ratings: (1)Supply voltage:–2.0V to 7.0V; (2)DC input voltage:–2.0V to 7.0V; (3)DC output current, per pin:–25mA to 25mA; (4)Storage temperature:–65℃ to 150℃; (5)Ambient temperature:–65℃ to 135℃; (6)Junction temperature:Ceramic packages, under bias:150℃, PQFP and RQFP packages, under bias:135℃.

Features

EPM7128STC100 features: (1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAXR architecture; (2)5.0-V in-system programmability (ISP) through the built-in; (3)IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices: ISP circuitry compatible with IEEE Std. 1532; (4)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (5)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (6)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (7)5-ns pin-to-pin logic delays with up to 175.4-MHz counter; (8)frequencies (including interconnect); (9)PCI-compliant devices available.